Shift instructions for microprocessor general-purpose registers often take two parameters as operand. The first operand specifies a designation register whose value is being shifted. The second operand is the count operand that specifies the amount by which the register is being shifted. The count operand may be a variable or a constant. If it is a variable, it may be specified as the value contained in another register or in a memory location. If it is a constant, it is defined by a predetermined value at coding time.
Some shift operands in a microprocessor instruction set may be limited to accepting a constant value as the count operand. Some shift instructions are further limited to shifting the register value by a large amount, e.g., shifting by bytes instead of by bits.
Previously, to simulate a shift by a variable amount, programmers have utilized instruction loops. For instance, a loop specifying a value of 1 for the shift count can be called repeatedly a variable amount of times to shift a register value by the desired amount.
In order to shift in bits instead of bytes, the programmers have previously looked at the microprocessor instruction set to find other shift instructions that allow shifting in bits and have utilized those instructions to simulate the desired shift operation in bits. For example, in the Intel® x86 architecture, the instruction for shifting a double quadword (where a word is 16 bits or 2 bytes) does not allow shifting in bits but the instruction for shifting a quadword does allow shifting in bits. Accordingly, in this architecture, some programmers who want to shift a double quadword register would write code to use the quadword shift instruction to generate missing bits from the other side and then would perform a logical ‘or’ operation on them to make the final result.
To illustrate this further, three more specific examples are provided for the Intel® x86 architecture. The Intel® SSE2 (Streaming SIMD Extensions 2) instruction set has PSLLDQ and PSRLDQ instructions for shift double quadword left logical and shift double quadword right logical respectively. These instructions shift a whole 128-bit register by a given constant value of bytes to left or right respectively. However, these instructions neither allow for variable shift operations nor allow for bitwise shift operations. Hence, to perform variable or bitwise 128-bit shift operations, programmers have to resort to other smaller shift operations in the SSE2 instruction set. Examples of such shift operations are the PSLLQ and PSRLQ shift operations that can variably shift a 64-bit value by a given bit value to left or right respectively.
The following three examples illustrate how programmers have used these smaller shift operations to simulate the shift double quadword to left or right operations. The first example shows shifting a double quadword to left by 5 bytes. The second example shows shifting a double quadword register to left by 10 bytes. As shown in these two examples, simulating either a variable byte shift or shifting by bits instead of bytes require different processing for the case where count operand is less than 8 when shifting in byes (less than 64 when shifting in bits) and the case where the operand is greater or equal to 8 (greater than equal to 64 when shifting in bits). The third example shows how shifting a double quadword may be implemented using a loop.